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PC312XDP512F0CFVR Datasheet(PDF) 702 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 702 Page - Freescale Semiconductor, Inc |
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702 / 1348 page  Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.21 704 Freescale Semiconductor 19.3.1.6 Debug Count Register (DBGCNT) Read: Anytime Write: Never 0x0026 76543210 R 0 CNT W Reset 0 — — ————— POR 00000000 Unimplemented or Reserved Figure 19-9. Debug Count Register (DBGCNT) Table 19-17. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer. Table 19-18 shows the correlation between the CNT bits and the number of valid data lines in the trace buffer. When the CNT rolls over to 0, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. Table 19-18. CNT Decoding Table TBF (DBGSR) CNT[6:0] Description 0 0000000 No data valid 0 0000001 32 bits of one line valid1 1 This applies to normal/loop1 modes when tracing from either CPU or XGATE only. 0 0000010 1 line valid 0 0000011 0000100 0000110 .. 1111100 1.5 lines valid1 2 lines valid 3 lines valid .. 62 lines valid 0 1111110 63 lines valid 1 0000000 64 lines valid; if using begin-trigger alignment, ARM bit will be cleared and the tracing session ends. 1 0000010 .. .. 1111110 64 lines valid, oldest data has been overwritten by most recent data |
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