THS7360 datasheet(33/43 Pages) TI

33 / 43 page

THS7360

www.ti.com

SLOS674 – JUNE 2010

EVALUATION MODULE

C26, C28, and/or C30) with 0-

Ω resistors works well.

To evaluate the THS7360, an evaluation module

Removing the 470-mF capacitors is optional, but

(EVM) is available. The THS7360EVM allows for

removing them from the EVM eliminates a few

testing the THS7360 in many different configurations.

picofarads of stray capacitance on each signal path

Inputs and outputs include BNC connectors and RCA

which may be desirable.

connectors commonly found in video systems, along

with 75-

Ω input termination resistors, 75-Ω series

The THS7360 incorporates an easy method to

source termination resistors, and 75-

Ω characteristic

configure the bypass modes and the disable modes.

impedance traces. Several unpopulated component

The use of JP4 controls the SD channels disable

pads are found on the EVM to allow for different input

feature; JP6 controls the SF channels disable feature;

and output configurations as dictated by the user.

JP3 controls the SD channels filter/bypass mode; and

This EVM is designed to be used with a single supply

JP5 controls the SF channels filter/bypass mode.

from 2.6 V up to 5 V.

Connection of JP4 and JP6 to GND applies 0 V to the

The EVM default input configuration sets all channels

disable pins and the THS7360 operates normally.

for dc input coupling. The input signal must be within

Moving JP4 to +VS causes the THS7360 SD

0 V to approximately 0.65 V for proper operation.

channels to be in disable mode, while moving JP6 to

Failure to be within this range saturates and/or clips

+VS causes the THS7360 SF channels to be in

the output signal. If the input range is beyond this, if

disable mode.

the signal voltage is unknown, or if coming from a

Connection of JP3 to GND places the THS7360 SD

current sink DAC, then ac input configuration is

channels in filter mode while moving JP3 to +VS

desired. This option is easily accomplished with the

places the THS7360 SD channels in bypass mode.

EVM by simply replacing the Z1 through Z6 0-Ω

Connection of JP5 to GND places the THS7360 SF

resistors with 0.1-mF capacitors.

channels in filter mode while moving JP5 to +VS

For an ac-coupled input and sync-tip clamp (STC)

places the THS7360 SF channels in bypass mode.

functionality commonly used for CVBS, s-video Y',

The filter selection is also easily accomplished by

component Y' signals, and R'G'B' signals, no other

using jumpers JP1 and JP2. JP1 controls the logic

changes are needed. However, if a bias voltage is

voltage for the filter 1 pin while JP2 controls the logic

needed after the input capacitor which is commonly

voltage for the filter 2 pin. Table 1 and Table 2 show

needed for s-video C', component P'B, and P'R, then a

the truth table for the filter selection and the

pull-up resistor should be added to the signal on the

appropriate

logic

for

3.3-V

and

5-V

operation,

EVM. This configuration is easily achieved by simply

respectively. The EVM also has a truth table printed

adding a resistor to any of the following resistor pads;

on it for easy reference.

RX7 to RX12. A common value to use is 10 M

Ω.

Note that even signals with embedded sync can also

Figure

49 shows

the

THS7360EVM

schematic.

use bias mode if desired.

Figure 51 and Figure 52 illustrate the two layers of

the EVM PCB, incorporating standard high-speed

The

EVM

default

output

configuration

sets

all

layout practices. Table 7 lists the bill of materials as

channels for ac output coupling. The 470-mF and

the board comes supplied from Texas Instruments.

0.1-mF capacitors work well for most ac-coupled

systems. However, if dc-coupled output is desired,

then replacing the 0.1-mF capacitors (C20, C22, C24,

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