TAS5611PHD datasheet(10/29 Pages) TI

10 / 29 page

TAS5611A

SLAS709 – JUNE 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

PVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as reference

VREG

VDD = 12 V

3.3

3.6

node, VREG

VI_CM

Analog comparator reference node, VI_CM

1.5

1.75

1.9

Operating, 50% duty cycle

IVDD

VDD supply current

Idle, reset mode

50% duty cycle

IGVDD_X

GVDD_x gate-supply current per half-bridge

Reset mode

1.5

50% duty cycle with recommended output

filter

IPVDD_X

Half-bridge supply current

Reset mode, No switching

540

ANALOG INPUTS

RIN

Input resistance

READY = HIGH

Ω

VIN

Maximum input voltage swing

IIN

Maximum input current

Voltage Gain (VOUT/VIN)

OSCILLATOR

Nominal, Master Mode

3.5

4.5

fOSC_IO+

AM1, Master Mode

FPWM × 10

3.0

3.4

3.8

MHz

AM2, Master Mode

2.6

3.35

VIH

High level input voltage

1.86

VIL

Low level input voltage

1.45

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

100

Ω

TJ = 25°C, excludes metallization

RDS(on)

resistance, GVDD = 12 V

Drain-to-source resistance, high side (HS)

100

Ω

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