MC68HC55SLASHD datasheet(21/40 Pages) FREESCALE

21 / 40 page

MC68HC55 Technical Data

Enable (Disable) Function

MC68HC55

Technical Data

Functional Description

Figure 4-2. State Diagram Notation

end of the condition or equation which must be true for a transition to

occur. The statement or statements after the slash are executed during

the transition to the next state. These state diagrams are not a complete

description of the entire MC68HC55. They are intended to include just

enough relevant data to understand the operation of the state machines

and basic DSI/D functions.

Figure 4-3

describes how SPI transfers lead to transmit FIFO push

operations or transfer abort actions. State transitions in this state

machine are synchronous with rising edges of the SPI clock. The initial

state, SP_IDLE, is entered asynchronously whenever internal reset

becomes active or the SPI chip select input goes high. Upon entry to the

idle state, the SPI_WRITE signal is deactivated and the SPI bit counter

is set to 7 (it will count down as bits are received).

When the SPI chip select goes low (active), the first SPI transfer will be

a command byte and the first bit indicates a write or read command. The

SPI_WRITE signal takes on the value of this first bit, and the state

machine enters the COMMAND_TRANSFER state, where the

remaining bits of the command byte are received. The last three bits of

the command set the initial value of the register pointer (update occurs

on the next SPI clock falling edge). After the command byte is complete,

the state machine advances to the SPI_BURST state, which remains

active until the SPI chip select goes high or the MC68HC55 is reset.

IDLE

STATE_1

ASYNCHRONOUS RESET/ACTION(S)

SYNCHRONOUS CONDITION/ACTION(S)

STATE TRANSITIONS OCCUR

ON POSEDGE OF XXX CLOCK

MC68HC55/D Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc