SC185LEVB datasheet(16/18 Pages) SEMTECH

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SC185

Figure 2 — Recommended PCB Layout (Top Layer)

Figure 3 — Bottom Layer Detail

PCB Layout Considerations

The layout diagram in Figure 2 shows a recommended

top-layer PCB for the SC185 and supporting components.

Figure 3 shows the bottom layer for this PCB. Fundamental

layout rules must be followed since the layout is critical

for achieving the performance specified in the Electrical

Characteristics table. Poor layout can degrade the

performance of the DC-DC converter and can contribute

to EMI problems, ground bounce, and resistive voltage

losses. Poor regulation and instability can result.

The following guidelines are recommended when

developing a PCB layout:

The input capacitor, C

IN should be placed as close to

the PVIN and PGND pins as possible. This capacitor

provides a low impedance loop for the pulsed currents

present at the buck converter’s input. Use short wide

traces to connect as closely to the IC as possible.

This will minimize EMI and input voltage ripple by

localizing the high frequency current pulses.

Keep the LX pin traces as short as possible to minimize

pickup of high frequency switching edges to other

parts of the circuit. C

OUT and L should be connected as

close as possible between the LX and PGND pins, with

a direct return to the PGND pin from C

OUT.

Route the output voltage feedback/sense path away

from the inductor and LX node to minimize noise and

magnetic interference.

Use a ground plane referenced to the SC185 PGND

pin. Use several vias to connect to the component

side ground to further reduce noise and interference

on sensitive circuit nodes.

If possible, minimize the resistance from the VOUT

and PGND pins to the load. This will reduce the

voltage drop on the ground plane and improve the

load regulation. And it will also improve the overall

efficiency by reducing the copper losses on the output

and ground planes.

Applications Information (continued)

GND

VIN

VOUT

VIN

GND

VOUT

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