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74ALVT16501 Datasheet(PDF) 11 Page - NXP Semiconductors

Part # 74ALVT16501
Description  18-bit universal bus transceiver; 3-state
PDF  20 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVT16501 Datasheet(HTML) 11 Page - NXP Semiconductors

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74ALVT16501_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 8 August 2005
11 of 20
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
[6]
ICC is measured with outputs pulled up to VCC or pulled down to ground.
[7]
This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8]
All typical values are at VCC = 3.3 V and Tamb = 25 °C.
[9]
This is the bus hold overdrive current required to force the input to the opposite logic state.
[10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 VtoVCC = 3.3 V ± 0.3 V
a transition time of 100
µs is permitted. This parameter is valid for Tamb =25 °C only.
11. Dynamic characteristics
Table 8:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.5 V ± 0.2 V [1]; CL = 30 pF
tPLH
propagation delay
An to Bn or Bn to An
see Figure 5
1.0
2.0
3.0
ns
LEAB to Bn or LEBA to An
see Figure 6
1.5
2.4
4.0
ns
CPAB to Bn or CPBA to An
see Figure 7
2.2
3.6
5.4
ns
tPHL
propagation delay
An to Bn or Bn to An
see Figure 5
1.4
2.1
3.5
ns
LEAB to Bn or LEBA to An
see Figure 6
1.5
2.3
4.0
ns
CPAB to Bn or CPBA to An
see Figure 7
1.9
3.2
5.4
ns
tPZH
output enable time to HIGH-level
see Figure 9
2.3
3.9
5.0
ns
tPZL
output enable time to LOW-level
see Figure 10
1.9
3.3
4.4
ns
tPHZ
output disable time from HIGH-level
see Figure 9
2.2
3.4
4.4
ns
tPLZ
output disable time from LOW-level
see Figure 10
1.6
2.8
3.4
ns
th(H)
hold time HIGH
An to CPAB or Bn to CPBA
see Figure 8
0
−1.2
-
ns
An to LEAB or Bn to LEAB
see Figure 8
+1.0
−0.5
-
ns
th(L)
hold time LOW
An to CPAB or Bn to CPBA
see Figure 8
+1.0
−0.4
-
ns
An to LEAB or Bn to LEAB
see Figure 8
2.0
1.0
-
ns
tsu(H)
set-up time HIGH
An to CPAB or Bn to CPBA
see Figure 8
1.9
0.4
-
ns
An to LEAB or Bn to LEBA
see Figure 8
0
−1.0
-
ns
tsu(L)
set-up time LOW
An to CPAB or Bn to CPBA
see Figure 8
2.5
1.2
-
ns
An to LEAB or Bn to LEBA
see Figure 8
+1.0
−0.5
-
ns
tWH
pulse width HIGH
CPAB or CPBA
see Figure 7
3.0
-
-
ns
LEAB or LEBA
see Figure 6
1.5
-
-
ns
tWL
pulse width LOW
CPAB or CPBA
see Figure 7
3.0
-
-
ns
fmax
maximum clock frequency
see Figure 7
150
-
-
MHz



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