Preliminary
8-37
RF2469
Rev A5 010717
8
Pin
Function
Description
Interface Schematic
15
LNA1 BYP
Logic control for LNA1 gain. A logic high (>2.4V) places LNA1 in the
high gain mode. A logic low (<0.3V) place LNA1 in the bypass mode.
16
ENABLE
A logic control for mixer and LO buffer. A logic high (>2.4V) turn the
mixer and LO buffer on. A logic low (<0.3V) disable the mixer and LO
buffer.
17
VCC1
Supply voltage for the mixer. An external resistor is place in series with
this pin to adjust the mixer current. A nominal value of 1000
Ω set the
mixer current to ~10mA. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
18
VCC1
Supply voltage for IC. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
19
LNA1 IN
RF input to LNA1. This pin is internally DC-biased and, if it is con-
nected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
20
GND
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias.
LNA1 BYP
32 k
Ω
ENABLE
32 k
Ω
LNA1 IN
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