Preliminary
12-3
RF2504
Rev A2 010117
12
Pin
Function
Description
Interface Schematic
1VCC1
Power supply connection for the VCO. This pin should be well
bypassed close to the package with a capacitor suitable for the fre-
quency of operation as well as a capacitor to minimize low frequency
noise from the voltage supply. The ground side of the capacitors should
connect immediately to ground plane.
2RES
Connection point for the resonator circuit. The resonator is an inductive
element. Changing the effective inductance, either physically or with a
varactor tuned circuit, will change the frequency of operation. Note that
all parasitics on the circuit board will contribute to the effective induc-
tance and will influence the frequency of operation. These effects
become more pronounced at higher operating frequencies. This pin
has DC bias present. A DC blocking capacitor, suitable for the fre-
quency of operation, should be used if the external circuitry has DC
present or presents a DC path to ground. See Application Example
Schematic and Theory of Operation section of this data sheet for
design details.
3GND1
Ground connection for the VCO. Keep traces physically short and con-
nect immediately to ground plane for best performance. In order to min-
imize load pulling, it is recommended that pin 3 have a different return
path to ground than pin 7 (i.e., separate vias to a common ground
plane).
See Pin 2
4NC
Not connected.
5VCC2
Power supply connection for the buffer amplifiers. This pin should be
well bypassed close to the package with a capacitor suitable for the fre-
quency of operation. The ground side of the capacitor should connect
immediately to ground plane.
6RF OUT
RF output pin. This is an open-collector output and must be biased
externally. A shunt bias/matching inductor to VCC and a series blocking/
matching capacitor are recommended. See Application Example Sche-
matic.
7GND3
Ground connection for the buffer amplifiers. Keep traces physically
short and connect immediately to ground plane for best performance.
In order to minimize load pulling, it is recommended that pin 3 have a
different return path to ground than pin 7 (i.e., separate vias to a com-
mon ground plane).
8PD
Power Down pin for the VCO and buffer amplifiers. A logic “low” (0.0 to
0.7V) turns the entire device off and supply current drops to less than
1
µA. A logic “high” (≥3.0V) turns the device on. Note that the voltage
on this pin should never exceed 5.5VDC.
Pins
3,4
Pin 2
To Buffer Amps
and Bias Ckts.
To Bias Ckts.
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