DAC7578SPWR datasheet(39/55 Pages) TI

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Amplifier

Resistor

String

DAC

Power-Down

Circuitry

Resistor

Network

OUT

DAC5578

DAC6578

DAC7578

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SBAS496A – MARCH 2010 – REVISED AUGUST 2010

For example: C3, C2, C1, and C0 = '0100' and DB14

CLR pin low clears the contents of all DAC registers

and DB13 = '11' represent a power-down condition

and all DAC buffers and replaces the code with the

with High-Z output impedance for a selected channel.

code determined by the clear code register. The clear

DB14 and DB13 = '01' represents a power-down

code register can be written to by applying the

condition with 1k

Ω output impedance, while DB14

commands showed in Table 14. The default setting of

and DB13 = '10' represents a power-down condition

the clear code register sets the output of all DAC

with 100k

Ω output impedance.

channels to 0V when the CLR pin is brought low. The

CLR pin is falling-edge triggered; therefore, the

Table 16. DAC Operating Modes

device exits clear code mode on the falling edge of

the acknowledge signal that follows LSDB of the next

PD1

PD0

write sequence. If the CLR pin is executed (brought

(DB14)

(DB13)

DAC OPERATING MODES

low) during a write sequence, this write sequence is

Power on selected DACs

aborted and the DAC registers and DAC buffers are

Power down selected DACs, 1k

Ω to GND

cleared as described above.

Power down selected DACs, 100k

Ω to GND

When performing a software reset of the device, the

Power down selected DACs, High-Z to GND

clear code register is reset to the default mode (DB5

= '0', DB4 = '0'). Setting the clear code register to

Spacer

DB4 = '1' and DB5 = '1' ignores any activity on the

external CLR pin.

SOFTWARE RESET FUNCTION

The DACx578 contains a software reset feature.

When the software reset feature is executed, the

device (all DAC channels) are reset to the power-on

reset code. All registers inside the device are reset to

the respective default settings. The DACx578 has an

additional feature of switching straight to high speed

mode after reset. Table 17 shows all the different

modes of the software reset function.

Table 17. Software Reset Modes

Figure 117. Output Stage During Power-Down

DB15

DB14

OPERATING MODES

Default Software reset. Equivalent to

Power-on-Reset

CLEAR CODE REGISTER AND CLR PIN

Software reset and set part in High Speed

The DACx578 contains a clear code register. The

Mode

clear code register can be accessed via the serial

Software reset and maintain High Speed

interface (I2C) and is user configurable. Bringing the

Mode state

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