AT90PWM3 datasheet(166/361 Pages) ATMEL

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4317J–AVR–08/10

AT90PWM2/3/2B/3B

• Bit 7:6 – PPRE11:0 : PSC 1 Prescaler Select

This two bits select the PSC input clock division factor.All generated waveform will be modified

by this factor.

• Bit 5 – PBFM1 : Balance Flank Width Modulation

When this bit is clear, Flank Width Modulation operates on On-Time 1 only.

When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1.

• Bit 4 – PAOC1B : PSC 1 Asynchronous Output Control B

When this bit is set, Fault input selected to block B can act directly to PSCOUT11 output. See

Section “PSC Clock Sources”, page 159

• Bit 3 – PAOC1A : PSC 1 Asynchronous Output Control A

When this bit is set, Fault input selected to block A can act directly to PSCOUT10 output. See

Section “PSC Clock Sources”, page 159

• Bit 2 – PARUN1 : PSC 1 Autorun

When this bit is set, the PSC 1 starts with PSC0. That means that PSC 1 starts :

•

when PRUN0 bit in PCTL0 register is set,

•

or when PARUN0 bit in PCTL0 is set and PRUN2 bit in PCTL2 register is set.

Thanks to this bit, 2 or 3 PSCs can be synchronized (motor control for example)

• Bit 1 – PCCYC1 : PSC 1 Complete Cycle

When this bit is set, the PSC 1 completes the entire waveform cycle before halt operation

requested by clearing PRUN1. This bit is not relevant in slave mode (PARUN1 = 1).

• Bit 0 – PRUN1 : PSC 1 Run

Writing this bit to one starts the PSC 1.

When set, this bit prevails over PARUN1 bit.

16.25.13 PSC 2 Control Register – PCTL2

Table 16-15. PSC 1 Prescaler Selection

PPRE11

PPRE10

Description PWM2/3

Description PWM2B/3B

No divider on PSC input clock

Divide the PSC input clock by 4

Divide the PSC input clock by 16

Divide the PSC input clock by 32

Divide the PSC clock by 64

Divide the PSC clock by 256

Bit

654

PPRE21

PPRE20

PBFM2

PAOC2B

PAOC2A

PARUN2

PCCYC2

PRUN2

PCTL2

Read/Write

R/W

Initial Value

AT90PWM3 Datasheet(PDF) 166 Page - ATMEL Corporation

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