SC824 datasheet(15/29 Pages) SEMTECH

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SC824

Applications Information (continued)

filter (R at least 100×R

IPRGM

, C large compared to the

Sample-and-Hold capacitance of the ADC) can prevent

corruption of the IPRGM pin voltage by the ADC. Any

noise introduced onto the IPRGM pin will be seen as

current noise at the SC824 output during CC regulation,

and can introduce errors in the termination current.

The IPRGM pin will see a brief (<1ms) pulse whenever the

charger turns on, just prior to enabling the output. This

pulse is part of the startup IPRGM pin-short (to ground)

test. When the charger first turns on, the processor should

allow time for this pulse prior to reading the IPRGM

voltage. See the section Short Circuit Protection.

MODE Pin Tri-level Logical Input

The MODE pin is designed to interface to a processor GPIO

port that is powered from a peripheral supply voltage as

low as 1.8V or as high as a fully charged battery. The pro-

cessor writes 0 to select MODE low-range, and 1 to select

high-range. The GPIO port is configured as an input to

select mid-range.

While driven high (V

MODE

> Min V

), the SC824 will operate

in USB High Power mode. While the MODE input voltage

is within its specified mid range (Min V

< V

ENB

< Max V

either by floating (by reconfiguring its GPIO as an input) or

by being externally forced, the SC824 will operate in USB

Low Power mode. While driven low (V

MODE

< Max V

), the

SC824 will operate in adapter mode.

When no charging source is present, while the charger is

disabled, or while operating in the monitor state (described

in a later section), the MODE pin enters a high impedance

state, suspending the tri-level functionality. Upon

recharge or re-enabling the charger, the MODE pin tri-

level interface is reactivated.

While the tri-level interface is active, the equivalent circuit

looking into the MODE pin is a variable resistance,

minimum 15kΩ, to an approximately 1V source. The input

will float to mid range whenever the external driver sinks

or sources less than 5μA. This is a common worst-case

characteristic of a high impedance GPIO, or a weak pull-up

or pull-down GPIO, configured as an input. The driving

GPIO must be able to sink or source at least 75μA to ensure

a low or high state, respectively, although the drive current

required is typically far less. (See the electrical character-

istics table.) Typically a processor GPIO port direction

defaults to input upon processor reset, or is high imped-

ance when unpowered. This is the ideal initial condition

for driving the MODE pin, since this will select USB Low

Power mode, which is the safest default mode with the

lowest fast charge current.

For fixed mode operation, this pin can be permanently

grounded to select low-range, left unconnected to select

mid-range, or permanently connected to a logical high

voltage source, such as BAT or a regulated peripheral

supply voltage, to select high-range.

Figure 3a — Termination Current Tolerance vs.

Programming Resistance, Low Resistance Range

2.5

3.5

4.5

5.5

6.5

100

105

110

115

IPRGM (k

Ω), R-tol = 1%

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

IPRGM (k

Ω), R-tol = 1%

Figure 3b — Termination Current Tolerance vs.

Programming Resistance, High Resistance Range

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