AT90PWM81 datasheet(13/325 Pages) ATMEL

13 / 325 page

7734P–AVR–08/10

AT90PWM81

Figure 3-4.

The Parallel Instruction Fetches and Instruction Executions

Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU opera-

tion using two register operands is executed, and the result is stored back to the destination register.

Figure 3-5.

Single Cycle ALU Operation

3.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each

have a separate program vector in the program memory space. All interrupts are assigned individual

enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status

automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves

software security. See the section “Memory Programming” on page 247 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vec-

tors. The complete list of vectors is shown in “Interrupts” on page 61. The list also determines the priority

levels of the different interrupts. The lower the address the higher is the priority level. RESET has the

highest priority, and next is PSC2 CAPT – the PSC2 Capture Event. The Interrupt Vectors can be moved

to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).

Refer to “Interrupts” on page 61 for more information. The Reset Vector can also be moved to the start of

the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-

Write Self-Programming” on page 232.

3.8.1

Interrupt Behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The

user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then

interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruc-

tion – RETI – is executed.

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

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