PIC18LF4331-ESLASHML datasheet(216/392 Pages) MICROCHIP

216 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 216

 2010 Microchip Technology Inc.

19.3.2

MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is

disabled. The Stop (P) and Start (S) bits will toggle

based on the Start and Stop conditions. Control of the

I2C bus may be taken when the P bit is set, or the bus

is Idle and both the S and P bits are clear.

In Master mode, the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<5:4> or

TRISD<3:2> bits. The output level is always low,

regardless of the value(s) in PORTC<5:4> or

PORTD<3:2>. So when transmitting data, a ‘1’ data bit

must have the TRISC<4> bit set (input) and a ‘0’ data

bit must have the TRISC<4> bit cleared (output). The

same scenario is true for the SCL line with the

TRISC<4> or TRISD<2> bit. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I2C module.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode Idle (SSPM<3:0> = 1011) or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

19.3.3

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when bit P (SSPSTAT<4>)

is set, or the bus is Idle and both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In Multi-Master mode, the SDA line must be monitored

to see if the signal level is the expected output level.

This check only needs to be done when a high level is

output. If a high level is expected and a low level is

present, the device needs to release the SDA and SCL

lines (set TRISC<5:4> or TRISD<3:2>). There are two

stages where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to retransfer the data at a

later time.

TABLE 19-3:

REGISTERS ASSOCIATED WITH I2C™ OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values

on Page:

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIE1

—

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE

SSPBUF

SSP Receive Buffer/Transmit Register

SSPADD

SSP Address Register (I2C mode)

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

SSPSTAT

SMP(1)

CKE(1)

D/A

R/W

TRISC(2)

PORTC Data Direction Register

TRISD(2)

PORTD Data Direction Register

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used by the SSP module in I2C mode.

Note 1:

Maintain these bits clear in I2C mode.

Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD.

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