PIC18LF4331-ESLASHML datasheet(37/392 Pages) MICROCHIP

37 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 37

PIC18F2331/2431/4331/4431

3.7.2

OSCILLATOR TRANSITIONS

The PIC18F2331/2431/4331/4431 devices contain

circuitry to prevent clocking “glitches” when switching

between clock sources. A short pause in the system

clock occurs during the clock switch. The length of this

pause is between 8 and 9 clock periods of the new

clock source. This ensures that the new clock source is

stable and that its pulse width will not be less than the

shortest pulse width of the two clock sources.

Clock transitions are discussed in greater detail in

Section 4.1.2 “Entering Power-Managed Modes”

3.8

Effects of Power-Managed Modes

on the Various Clock Sources

When PRI_IDLE mode is selected, the designated

primary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator using

the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin,

if used by the oscillator) will stop oscillating.

When the device executes a SLEEP instruction, the

system is switched to one of the power-managed

modes, depending on the state of the IDLEN and

SCS<1:0> bits of the OSCCON register. See

Section 4.0 “Power-Managed Modes”

for details.

secondary

clock

modes

(SEC_RUN

and

SEC_IDLE), the Timer1 oscillator is operating and

providing the system clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1.

In internal oscillator modes (RC_RUN and RC_IDLE),

the internal oscillator block provides the system clock

source. The INTRC output can be used directly to

provide the system clock and may be enabled to

support various special features, regardless of the

power-managed mode (see Section 23.2 “Watchdog

Timer (WDT)”

through Section 23.4 “Fail-Safe Clock

Monitor”

). The INTOSC output at 8 MHz may be used

directly to clock the system, or may be divided down

first. The INTOSC output is disabled if the system clock

is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a Real-

Time Clock. Other features may be operating that do

not require a system clock source (i.e., SSP slave,

INTx pins, A/D conversions and others).

3.9

Power-up Delays

Power-up delays are controlled by two timers, so that no

external Reset circuitry is required for most applications.

The delays ensure that the device is kept in Reset until

the device power supply is stable under normal

circumstances, and the primary clock is operating and

stable. For additional information on power-up delays,

see Section 5.3 “Power-on Reset (POR)” through

Section 5.4 “Brown-out Reset (BOR)”

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 26-8), if enabled, in Configuration Register 2L.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the crys-

tal oscillator is stable (LP, XT and HS modes). The OST

does this by counting 1024 oscillator cycles before

allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, the

device is kept in Reset for an additional 2 ms, following

the HS mode OST delay, so the PLL can lock to the

incoming clock frequency.

TABLE 3-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode

OSC1 Pin

OSC2 Pin

RC, INTIO1

Floating, external resistor

should pull high

At logic low (clock/4 output)

RCIO, INTIO2

Floating, external resistor

should pull high

Configured as PORTA, bit 6

ECIO

Floating, pulled by external clock

Configured as PORTA, bit 6

Floating, pulled by external clock

At logic low (clock/4 output)

LP, XT and HS

Feedback inverter disabled at

quiescent voltage level

Feedback inverter disabled at

quiescent voltage level

Note:

See Table 5-1 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.

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