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PIC18LF4331-E/ML Datasheet(PDF) 279 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 279 Page - Microchip Technology |
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279 / 392 page ![]() 2010 Microchip Technology Inc. DS39616D-page 279 PIC18F2331/2431/4331/4431 23.5 Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. The user program memory is divided into five blocks. One of these is a Boot Block of 512 bytes. The remainder of the memory is divided into four blocks on binary boundaries. Each of the five blocks has three code protection bits associated with them. They are: • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) Figure 23-5 shows the program memory organization for 8 and 16-Kbyte devices, and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 23-3. FIGURE 23-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431 TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — —CP3(1) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — —WRT3(1) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F2331/4331 devices; maintain this bit set. MEMORY SIZE/DEVICE Block Code Protection Controlled By: 8Kbytes (PIC18F2331/4331) Address Range 16 Kbytes (PIC18F2431/4431) Address Range Boot Block 0000h 0FFFh Boot Block 0000h 01FFh CPB, WRTB, EBTRB Block 0 0200h 0FFFh Block 0 0200h 0FFFh CP0, WRT0, EBTR0 Block 1 1000h 1FFFh Block 1 1000h 1FFFh CP1, WRT1, EBTR1 Unimplemented Read ‘0’s Block 2 2000h 2FFFh CP2, WRT2, EBTR2 3FFFh Block 3 3000h 3FFFh CP3, WRT3, EBTR3 |
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