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PIC18LF4331-E/ML Datasheet(PDF) 354 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 354 Page - Microchip Technology |
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354 / 392 page  PIC18F2331/2431/4331/4431 DS39616D-page 354 2010 Microchip Technology Inc. FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) TABLE 26-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units Conditions 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 20 — ns 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 40 — ns 75 TdoR SDO Data Output Rise Time PIC18FXX31 — 25 ns PIC18LFXX31 — 45 ns 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXX31 — 25 ns PIC18LFXX31 — 45 ns 79 TscF SCK Output Fall Time — 25 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge PIC18FXX31 — 50 ns PIC18LFXX31 — 100 ns 81 TdoV2scH, TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns SCK (CKP = 0) SCK (CKP = 1) SDO SDI 81 74 75, 76 78 80 MSb 79 73 MSb In bit 6 - - - - - -1 LSb In bit 6 - - - -1 LSb |
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