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PIC18LF4331-E/ML Datasheet(PDF) 361 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 361 Page - Microchip Technology |
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361 / 392 page  2010 Microchip Technology Inc. DS39616D-page 361 PIC18F2331/2431/4331/4431 TABLE 26-20: A/D CONVERTER CHARACTERISTICS PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Device Supply AVDD Analog VDD Supply VDD – 0.3 — VDD + 0.3 V AVSS Analog VSS Supply VSS – 0.3 — VSS + 0.3 V IAD Module Current (during conversion) — — 500 250 — — A A VDD = 5V VDD = 2.5V IADO Module Current Off — — 1.0 A AC Timing Parameters A10 FTHR Throughput Rate — — — — 200 75 ksps ksps VDD = 5V, single channel VDD < 3V, single channel A11 TAD A/D Clock Period 385 1000 — — 20,000 20,000 ns ns VDD = 5V VDD = 3V A12 TRC A/D Internal RC Oscillator Period — — — 500 750 10000 1500 2250 20000 ns ns ns PIC18F parts PIC18LF parts AVDD < 3.0V A13 TCNV Conversion Time(1) 12 12 12 TAD A14 TACQ Acquisition Time(2) 2(2) —— TAD A16 TTC Conversion Start from External 1/4 TCY —— Reference Inputs A20 VREF Reference Voltage for 10-Bit Resolution (VREF+ – VREF-) 1.5 1.8 — — AVDD – AVSS AVDD – AVSS V V VDD 3V VDD < 3V A21 VREFH Reference Voltage High (AVDD or VREF+) 1.5V — AVDD VVDD 3V A22 VREFL Reference Voltage Low (AVSS or VREF-) AVSS —VREFH – 1.5V V A23 IREF Reference Current — — 150 A 75 A — — VDD = 5V VDD = 2.5V Analog Input Characteristics A26 VAIN Input Voltage(3) AVSS – 0.3 — AVDD + 0.3 V A30 ZAIN Recommended Impedance of Analog Voltage Source —— 2.5 k A31 ZCHIN Analog Channel Input Impedance — — 10.0 k VDD = 3.0V DC Performance A41 NR Resolution 10 bits — A42 EIL Integral Nonlinearity — — < 1LSb VDD 3.0V VREFH 3.0V A43 EIL Differential Nonlinearity — — < 1LSb VDD 3.0V VREFH 3.0V A45 EOFF Offset Error — 0.5 < 1.5 LSb VDD 3.0V VREFH 3.0V A46 EGA Gain Error — 0.5 < 1.5 LSb VDD 3.0V VREFH 3.0V A47 — Monotonicity(4) guaranteed — VDD 3.0V VREFH 3.0V Note 1: Conversion time does not include acquisition time. See Section 21.0 “10-Bit High-Speed Analog-to-Digital Converter (A/D) Module” for a full discussion of acquisition time requirements. 2: In Sequential modes, TACQ should be 12 TAD or greater. 3: For VDD < 2.7V and temperature below 0°C, VAIN should be limited to range < VDD/2. 4: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. |
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