PIC18LF4331-ESLASHML datasheet(108/392 Pages) MICROCHIP

108 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 108

 2010 Microchip Technology Inc.

10.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three peripheral

interrupt priority registers (IPR1, IPR2 and IPR3).

Using the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

U-0

R/W-1

—

ADIP

RCIP

TXIP

SSPIP

CCPIP

TMR2IP

TMR1IP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented:

Read as ‘0’

bit 6

ADIP:

A/D Converter Interrupt Priority bit

=High priority

= Low priority

bit 5

RC1IP:

EUSART Receive Interrupt Priority bit

=High priority

= Low priority

bit 4

TX1IP:

EUSART Transmit Interrupt Priority bit

=High priority

= Low priority

bit 3

SSP1IP:

Synchronous Serial Port Interrupt Priority bit

=High priority

= Low priority

bit 2

CCP1IP:

CCP1 Interrupt Priority bit

=High priority

= Low priority

bit 1

TMR2IP:

TMR2 to PR2 Match Interrupt Priority bit

=High priority

= Low priority

bit 0

TMR1IP:

TMR1 Overflow Interrupt Priority bit

=High priority

= Low priority

PIC18LF4331-E/ML Datasheet(PDF) 108 Page - Microchip Technology

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