PIC18LF4331-ESLASHML datasheet(153/392 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39616D-page 153

PIC18F2331/2431/4331/4431

17.1

Input Capture

The Input Capture (IC) submodule implements the

following features:

• Three channels of independent input capture

(16-bits/channel) on the CAP1, CAP2 and CAP3

pins

• Edge-Trigger, Period or Pulse-Width

Measurement Operating modes for each channel

• Programmable prescaler on every input capture

channel

• Special Event Trigger output (IC1 only)

• Selectable noise filters on each capture input

Input Channel 1 (IC1) includes a Special Event

Trigger that can be configured for use in Velocity

Measurement mode. Its block diagram is shown in

Figure 17-2. IC2 and IC3 are similar, but lack the

Special Event Trigger features or additional velocity

measurement logic. A representative block diagram is

shown in Figure 17-3. Please note that the time base

is Timer5.

FIGURE 17-2:

INPUT CAPTURE BLOCK DIAGRAM FOR IC1

CAP1BUF/VELR(1)

CAP1 Pin

CAP1M<3:0> Q Clocks

FLTCK<2:0>

VELM

TMR5

Timer5 Reset

Timer

Reset

Control

Clock

Q Clocks

CAP1M<3:0>

MUX

First Event

CAP1BUF_clk

Reset

IC1_TR

Timer5 Logic

Reset

Control

Reset

velcap(2)

Clock/

Reset/

Interrupt

Decode

Logic

Special

Event Trigger

Reset

IC1IF

Note 1:

CAP1BUF register is reconfigured as VELR register when QEI mode is active.

QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.

Prescaler

1, 4, 16

Noise

Filter

and

Mode

Select

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