PIC18LF4331-ESLASHML datasheet(159/392 Pages) MICROCHIP

159 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 159

PIC18F2331/2431/4331/4431

17.1.5

ENTERING INPUT CAPTURE MODE

AND CAPTURE TIMING

The following is a summary of functional operation

upon entering any of the Input Capture modes:

After the module is configured for one of the

Capture modes by setting the Capture Mode

Select bits (CAPxM<3:0>), the first detected

edge captures the Timer5 value and stores it in

the CAPxBUF register. The timer is then reset

(depending on the setting of CAPxREN bit) and

starts to increment according to its settings (see

Figure 17-4, Figure 17-5 and Figure 17-6).

On all edges, the capture logic performs the

following:

Input Capture mode is decoded and the

active edge is identified.

The CAPxREN bit is checked to determine

whether Timer5 is reset or not.

On every active edge, the Timer5 value is

recorded in the Input Capture Buffer

(CAPxBUF).

Reset Timer5 after capturing the value of

the timer when the CAPxREN bit is

enabled. Timer5 is reset on every active

capture edge in this case.

On all continuing capture edge events,

repeat steps (a) through (d) until the opera-

tional mode is terminated, either by user

firmware, POR or BOR.

The timer value is not affected when switch-

ing into and out of various Input Capture

modes.

17.1.6

TIMER5 RESET

Every input capture trigger can optionally reset

(TMR5). The Capture Reset Enable bit, CAPxREN,

gates the automatic Reset of the time base of the cap-

ture event with this enable Reset signal. All capture

events reset the selected timer when CAPxREN is set.

Resets are disabled when CAPxREN is cleared (see

Figure 17-4, Figure 17-5 and Figure 17-6).

17.1.7

IC INTERRUPTS

There are four operating modes for which the IC

module can generate an interrupt and set one of the

Interrupt Capture Flag bits (IC1IF, IC2QEIF or

IC3DRIF). The interrupt flag that is set depends on the

channel in which the event occurs. The modes are:

• Edge Capture

(CAPxM<3:0> = 0001, 0010, 0011 or 0100)

• Period Measurement Event (CAPxM<3:0> = 0101)

• Pulse-Width Measurement Event

(CAPxM<3:0> = 0110 or 0111)

• State Change Event (CAPxM<3:0> = 1000)

The timing of interrupt and Special Event Trigger

events is shown in Figure 17-7. Any active edge is

detected on the rising edge of Q2 and propagated on

the rising edge of Q4 rising edge. If an active edge

happens to occur any later than this (on the falling edge

of Q2, for example), then it will be recognized on the

next Q2 rising edge.

FIGURE 17-7:

CAPx INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER

Note:

The CAPxREN bit has no effect in

Pulse-Width Measurement mode.

Note:

The Special Event Trigger is generated

only in the Special Event Trigger mode on

the CAP1 input (CAP1M<3:0> = 1110

and 1111). IC1IF interrupt is not set in this

mode.

OSC

CAP1 Pin

IC1IF

TMR5

TMR5 Reset

XXXX

0000

0001

TMR5ON(1)

Note 1:

Timer5 is only reset and enabled (assuming TMR5ON = 0 and T5MOD = 1) when the Special Event Trigger Reset is

enabled for the Timer5 Reset input. The TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following

the event capture. With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger

Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must

be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111).

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