© Semiconductor Components Industries, LLC, 2006

October, 2006 − Rev. 0

1

Publication Order Number:

NB3N502DEVB/D

NB3N502DEVB

NB3N502 Evaluation Board

User’s Manual

Description

The NB3N502 Evaluation Board was designed to provide

a flexible and convenient platform to quickly evaluate,

characterize and verify the performance and operation of the

NB3N502 PLL Clock Multiplier. This user’s manual

provides detailed information on the board’s contents,

layout and use, and it should be used in conjunction with the

NB3N502 data sheet which contains full technical details on

device specifications and operation (www.onsemi.com).

Board Features

NB3N502 in the SOIC−8 Package

or Surface Mount Crystal

Output Interfaces

Multiplier Select Pins, Minimizing Excess Cabling

This Evaluation Board Manual Contains

Figure 1. NB3N502 Evaluation Board

http://onsemi.com