LM48520TL datasheet(13/18 Pages) NSC

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LOAD = IIND(AVG) x (1 - DC)

(6)

Where "DC" is the duty cycle of the application. The switch

current can be found by:

SW = IIND(AVG) + 1/2 (IRIPPLE)

(7)

Inductor ripple current is dependent on inductance, duty cy-

cle, input voltage and frequency:

RIPPLE = DC x (VIN-VSW) / (f x L)

(8)

combining all terms, we can develop an expression which al-

lows the maximum available load current to be calculated:

LOAD(max) = (1–DC)x(ISW(max)–DC(VIN-VSW))/fL

(9)

The equation shown to calculate maximum load current takes

into account the losses in the inductor or turn-OFF switching

losses of the FET and diode.

DESIGN PARAMETERS V

SW AND ISW

The value of the FET "ON" voltage (referred to as V

SW in

equations 4 thru 7) is dependent on load current. A good ap-

proximation can be obtained by multiplying the "ON Resis-

tance" of the FET times the average inductor current.

FET on resistance increases at V

IN values below 5V, since

the internal N-FET has less gate voltage in this input voltage

range (see Typical Performance Characteristics curves).

Above V

IN = 5V, the FET gate voltage is internally clamped to

5V.

The maximum peak switch current the device can deliver is

dependent on duty cycle. For higher duty cycles, see Typical

Performance Characteristics curves.

INDUCTOR SUPPLIERS

The recommended inductor for the LM48520 is the

NR8040T6R8N from Taiyo Yuden. When selecting an induc-

tor, make certain that the continuous current rating is high

enough to avoid saturation at peak currents, where:

IND = (PV1 / VDD) x ILOAD(BOOST)

(10)

A suitable core type must be used to minimize core (switch-

ing) losses, and wire power losses must be considered when

selecting the current rating.

PCB Layout Guidelines

High frequency boost converters require very careful layout

of components in order to get stable operation and low noise.

All components must be as close as possible to the LM48520

device. It is recommended that a four layer PCB be used so

that internal ground planes are available.

Some additional guidelines to be observed (all designators

are referencing Figure 1):

1. Keep the path between L1, D1, and Co extremely short.

Parasitic trace inductance in series with D1 and Co will in-

crease noise and ringing.

2. The feedback components R1, R2 and Cf1 must be kept

close to the FB pin to prevent noise injection on the FB pin

trace.

3. Since the external components of the boost converter

are switching, L1 and D1 should be kept away from the input

traces to prevent the noise from injecting into the input.

4. The power supply bypass capacitors, Cs1 and Cs2

should be placed as close to the LM48520 device as possible.

GROUNDING GUIDELINES

There are three grounds on the LM48520, GND, SW_GND,

and PGND. When laying out the PCB, it is critical to connect

the grounds as close to the device as possible. The simplest

way to do that is to place vias close to the GND, SW_GND,

and PGND bumps and connect the GND, SW_GND, and

PGND vias using a single ground plane in an inner layer of

the PCB.

LM48520TL Datasheet(PDF) 13 Page - National Semiconductor (TI)

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