MB90583CPF datasheet(58/112 Pages) FUJITSU

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MB90580C Series

DS07-13710-7E

10. DTP/External Interrupts

The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX

CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the

requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels

(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts

on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.

(1) Register configuration

(2) Block Diagram

• Interrupt/DTP enable register

bit

6543210

Address

: 0000030H

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

ENIR

Access

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

(0)

• Interrupt/DTP source register

bit

151413121110

Address

: 0000031H

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

EIRR

Access

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

(X)

• Request level setting register (lower)

bit

6543210

Address

: 0000032H

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

ELVR lower

Access

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

(0)

• Request level setting register (upper)

bit

151413121110

Address

: 0000033H

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

ELVR upper

Access

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

(0)

Interrupt/DTP enable register

Interrupt/DTP source register

Request level setting register

Gate

Source F/F

Edge detect circuit

Request input

F2MC-16LX bus

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