LU82551IT datasheet(39/102 Pages) INTEL

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Networking Silicon — 82551IT

Datasheet

5.6.1

Full Duplex

When operating in full duplex mode the 82551IT can transmit and receive frames simultaneously.

Transmission starts regardless of the state of the internal receive path. Reception starts when the

internal PHY detects a valid frame on the receive differential pair of the PHY.

The 82551IT operates in either half duplex mode or full duplex mode. For proper operation, both

the 82551IT CSMA/CD module and the PHY unit must be set to the same duplex mode. The

CSMA duplex mode is set by the 82551IT Configure command or forced by the settings in the

PHY unit’s registers.

The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by

setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the

internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the

duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto-

Negotiation.

The selection of duplex operation (full or half) and flow control is done in two levels: MAC and

PHY. The MAC duplex selection is done only through the CSMA configuration mechanism (in

other words, the Configure command in software).

5.6.2

Flow Control

The 82551IT supports IEEE 802.3x frame-based flow control frames in both full duplex and half

duplex switched environments. The 82551IT flow control feature is not intended to be used in

shared media environments.

The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation

algorithm or through the Management Data Interface.

5.6.3

Address Filtering Modifications

The 82551IT can be configured to ignore one bit when checking for its Individual Address (IA) on

incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least

significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority

indication bit. When configured to do so, the 82551IT passes any frame that matches all other 47

address bits of its IA, regardless of the U/L bit value.

This configuration only affects the 82551IT specific IA and not multicast, multi-IA or broadcast

address filtering. The 82551IT does not attribute any priority to frames with this bit set, it simply

passes them to memory regardless of this bit.

5.6.4

VLAN Support

The 82551IT controller supports the VLAN standard as currently defined by the IEEE 802.1

committee. All VLAN receive flows will be implemented by software. The 82551IT supports the

reception of long frames, specifically frames longer than 1518 bytes, including CRC, if software

sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are

discarded.

LU82551IT Datasheet(PDF) 39 Page - Intel Corporation

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