M48T512Y, M48T512V

Operating modes

Doc ID 5747 Rev 6

9/23

2.2

WRITE mode

The M48T512Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)

are low state after the address inputs are stable.

The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE

is terminated by the earlier rising edge of W or E. The addresses must be held valid

should be kept high during WRITE cycles to avoid bus contention; although, if the output bus

falls.

Figure 5.

WRITE AC waveforms, WRITE enable controlled

Figure 6.

WRITE AC waveforms, chip enable controlled

AI02386

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A18

E

W

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI02387

tAVAV

tEHAX

tDVEH

A0-A18

E

W

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT