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Low Power Features

Datasheet

2.1.1.3

Thread C1/MWAIT Power-down State

C1/MWAIT is a low-power state entered when the processor thread executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor to return to the

C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,

N-Z, for more information.

2.1.1.4

Thread C2 State

Individual threads of the dual-threaded processor can enter the C2 state by initiating a

P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not

issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also

asserted.

While in the C2 state, the processor will process bus snoops and snoops from the

other thread. The processor thread will enter a snoopable sub-state (not shown in

Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5

Thread C4 State

Individual threads of the processor can enter the C4 state by initiating a P_LVL4 I/O

read to the P_BLK or an MWAIT(C4) instruction. If both processor threads are in C4,

the central power management logic will request that the entire processor enter the

Deeper Sleep package low-power state (see Section 2.1.2.6).

To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing

and Intel Enhanced Deeper Sleep state fields must be configured in the software

programmable MSR bit.

2.1.2

Package Low-power State Descriptions

The following state descriptions assume that both threads are in a common low power

state. For cases when only one thread is in a low power state (see Section 2.1.1).

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the

Normal state when the threads are in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each thread of the processors enters the Stop-

Grant state within 1384 bus clocks after the response phase of the processor-issued

Stop-Grant Acknowledge special bus cycle. When the STPCLK# pin is de-asserted, the

core returns to its previous low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to VCCP) for minimum power drawn by the

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