ST662AB, ST662AC

Application circuit

Doc ID 5068 Rev 8

11/20

7

Application circuit

Based on fast charge/discharge of capacitors, this circuit involves high di/dt values limited

inductive paths and place capacitors as close as possible to the device.

A good layout design is strongly recommended for noise reason. For best performance, use

very short connections to the capacitors and the values shown in Table 7.

C3 and C4 must have low ESR in order to minimize the output ripple. Their values can be

reduced to 2 µF and 1 µF, respectively, when using ceramic capacitors, but must be of 10 µF

or larger if aluminium electrolytic are chosen.

C5 must be placed as close to the device as possible and could be omitted if very low output

noise performance are not required.

Figure 15 and Figure 16 show, respectively, our EVALUATION kit layout and the relatively.

Figure 15.

KIT layout