Rev. 4 | Page 32 of 44 | www.onsemi.com

FS6131

Clicking on Solution #3 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key

settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be

saved to a file, two formats are available: a text format for viewing and a data format for loading into the FS6131.

Table 21: Sample Text Output

ON SEMICONDUCTOR - FS6131 Solution Text File

Created: Today’s Date, Today’s Time

Line-Locked / Genlock Mode

Desired Multiple = 800

Source = 0.0315MHz Reference Pin

External Loop Filter C1 = 4700pF R = 47kOhms

Crystal Oscillator Voltage Tune Disabled

Output Stage = CMOS

Reference Divider = 1

Feedback Divider = 800

Post Divider

= 4

Charge Pump (uA) = 10

EXTLF

= 1

XLVTEN

= 0

XCT

= 7

CMOS

= 1

Register 0 = 1H (1)

Register 1 = 40H (64)

Register 2 = 2H (2)

Register 3 = 20H (32)

Register 4 = 3H (3)

Register 5 = 26H (38)

Register 6 = 0H (0)

Register 7 = 17H (23)

11.0 Applications Information

A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several

undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the

board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal

reflections.

11.1 PECL Output Mode

If a PECL interface is desired, the transmission line must be terminated using a Thévenin, or dual, termination. The output stage can

only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source

current is provided by the pull-up resistor that is part of the Thévenin termination.