MAX5940CESA datasheet(6/15 Pages) MAXIM

6 / 15 page

IEEE 802.3af PD Interface Controller

For Power-Over-Ethernet

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Pin Description

MAX5940A/

MAX5940C

MAX5940B/

MAX5940D

NAME

FUNCTION

1, 7

—

N.C.

No Connection. Not internally connected.

—1

UVLO

Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its

threshold, the device enters power mode. Connect UVLO to VEE to use the default

undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a

threshold externally. The series resistance value of the external resistors must add to 25.5k

(±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull

UVLO to between VTH,G,UVLO and VREF,UVLO.

RCLASS

Classification Setting. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1

and 2).

GATE

Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters

power mode. Connect an external 100V ceramic capacitor (CGATE) from GATE to OUT to

program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection

and classification functions operate normally when GATE is pulled to VEE.

VEE

Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect

VEE to -48V.

OUT

Output Voltage. Drain of the integrated isolation N-channel power MOSFET.

PGOOD

Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.

PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above

VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND).

Connect PGOOD to the ON pin of a downstream DC-DC converter.

—7

PGOOD

Power-Good Indicator Output, Active-Low, Open-Drain.

PGOOD is referenced to VEE.

PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE.

Otherwise,

PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream

DC-DC converter.

GND

Ground. GND is the positive input terminal.

Detailed Description

Operating Modes

The PD front-end section of the MAX5940_ operates in 3

different modes, PD detection signature, PD classifica-

tion, and PD power, depending on its input voltage (VIN =

GND - VEE). All voltage thresholds are designed to oper-

ate with or without the optional diode bridge while still

complying with the IEEE 802.3af standard (see Figure 4).

Detection Mode (1.4V

≤ VIN ≤ 10.1V)

In detection mode, the power source equipment (PSE)

applies two voltages on VIN in the range of 1.4V to 10.1V

(1V step minimum), and then records the current mea-

surements at the two points. The PSE then computes

ΔV/ΔI to ensure the presence of the 25.5kΩ signature

resistor. In this mode, most of the MAX5940_ internal cir-

cuitry is off and the offset current is less than 10µA.

If the voltage applied to the PD is reversed, install pro-

tection diodes on the input terminal to prevent internal

damage to the MAX5940_ (see the Typical Application

Circuits). Since the PSE uses a slope technique (

ΔV/ΔI)

to calculate the signature resistance, the DC offset due

to the protection diodes is subtracted and does not

affect the detection process.

MAX5940CESA Datasheet(PDF) 6 Page - Maxim Integrated Products

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