13892 datasheet(44/161 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

PROGRAMMABILITY

Table 10. SPI Interface Timing Specifications

Parameter

Description

T min (ns)

TSELSU

Time CS has to be high before the first rising edge of CLK

TSELHLD

Time CS has to remain high after the last falling edge of CLK

TSELLOW

Time CS has to remain low between two transfers

TCLKPER

Clock period of CLK

TCLKHIGH

Part of the clock period where CLK has to remain high

TCLKLOW

Part of the clock period where CLK has to remain low

TWRTSU

Time MOSI has to be stable before the next rising edge of CLK

4.0

TWRTHLD

Time MOSI has to remain stable after the rising edge of CLK

4.0

TRDSU

Time MISO will be stable before the next rising edge of CLK

4.0

TRDHLD

Time MISO will remain stable after the falling edge of CLK

4.0

TRDEN

Time MISO needs to become active after the rising edge of CS

4.0

TRDDIS

Time MISO needs to become inactive after the falling edge of CS

4.0

Notes

34.

This table reflects a maximum SPI clock frequency of 26 MHz

Table 11. SPI Interface Logic IO Specifications

Parameter

Condition

Min

Typ

Max

Units

Input Low CS, MOSI, CLK

0.3*SPIVCC

Input High CS, MOSI, CLK

0.7*SPIVCC

SPIVCC+0.3

Output Low MISO, INT

Output sink 100

μA

0.2

Output High MISO, INT

Output source 100

μA

SPIVCC-0.2

SPIVCC

SPIVCC Operating Range

1.75

3.1

MISO Rise and Fall Time

CL = 50 pF, SPIVCC = 1.8 V

SPIDRV[1:0] = 00 (default)

SPIDRV[1:0] = 01

6.0

SPIDRV[1:0] = 10

High Z

SPIDRV[1:0] = 11

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