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P89LPC9331 Datasheet(PDF) 54 Page - NXP Semiconductors |
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P89LPC9331 Datasheet(HTML) 54 Page - NXP Semiconductors |
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54 / 94 page ![]() P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 10 January 2011 54 of 94 NXP Semiconductors P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 7.28 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal 400 kHz watchdog oscillator or low speed crystal oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 22 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few μs to a few seconds. Please refer to the P89LPC9331/9341/9351/9361 User manual for more details. 7.29 Additional features 7.29.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 7.29.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 22. Watchdog timer in Watchdog mode (WDTE = 1) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDCON (A7H) SHADOW REGISTER PRESCALER 002aae015 8-BIT DOWN COUNTER WDL (C1H) watchdog oscillator crystal oscillator PCLK XTALWD ÷32 0 1 0 1 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1) |
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