Operating modes

M48Z128, M48Z128Y, M48Z128V

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Doc ID 2426 Rev 5

Table 4.

WRITE mode AC characteristics

2.3

Data retention mode

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

inputs are treated as “Don't care.”

If power fail detection occurs during a valid access, the memory cycle continues to

source which preserves data.

The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of

For more information on battery storage life refer to the application note AN1012.

Symbol

1.

noted).

M48Z128/Y

M48Z128/Y/V

M48Z128/Y/V

Unit

–70

–85

–120

Min

Max

Min

Max

Min

Max

WRITE cycle time

70

85

120

ns

Address valid to WRITE enable Low

0

0

0

ns

Address valid to chip enable low

0

0

0

ns

WRITE enable pulse width

55

65

85

ns

Chip enable low to chip enable high

55

75

100

ns

WRITE enable high to address transition

5

5

5

ns

Chip enable high to address transition

15

15

15

ns

Input valid to WRITE enable high

30

35

45

ns

Input valid to chip enable high

30

35

45

ns

WRITE enable high to input transition

0

0

0

ns

Chip enable high to input transition

10

10

10

ns

(2)(3)

2.

3.

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z

25

30

40

ns

Address valid to WRITE enable high

65

75

100

ns

Address valid to chip enable high

65

75

100

ns

(2)(3)

WRITE enable high to output transition

5

5

5

ns