4

SERIAL DATA CLOCK

t

PWL

Loaded Last

Logic ’1’

Loaded

First

BIT 7

BIT 6

BIT 1

BIT 0

t

DH

SERIAL DATA IN

(ONE 8-BIT WORD)

8th

Clock

Pulse

Next

Clock

Pulse

LOAD/LATCH

LOAD/LATCH

Fig.4 Serial Control Data Loading Diagram

Data is loaded to the FX009A on the rising edge of the

Serial Clock.

Loaded data is executed on the falling

(rising) edge of the Load/Latch (Load/Latch) pulse. Table

1 shows the format of each 4-bit Address word, Table 2

shows the format of each Gain Control word with Figure 4

describing the data loading operation and timing.

The gain of each amplifier block (Channel 1 to Channel 8)

in the FX009A is set by a separate 8-bit data word ( bit 7

to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit

7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded

to the Control Data Input in serial format using the external

data clock.

Table 1 Address Word Format

Bit 7

Bit 6

Bit 5

Bit 4

Channel

MSB

LSB

Selected

10

0

0

1

10

0

1

2

10

1

0

3

10

1

1

4

11

0

0

5

11

0

1

6

11

1

0

7

11

1

1

8

Table 2 Gain Control Word Format

Bit 3

Bit2

Bit 1

Bit 0

Stage 1 to 7

Stage 8

MSB

LSB

(0.43dB)

(2.0dB)

0000

Powersave

Powersave

0001

-3.0

-14.0

dB

0010

-2.571

-12.0

dB

0011

-2.143

-10.0

dB

0100

-1.714

-8.0

dB

0101

-1.286

-6.0

dB

0110

-0.857

-4.0

dB

0111

-0.428

-2.0

dB

1000

0

0

dB

1001

0.428

2.0

dB

1010

0.857

4.0

dB

1011

1.286

6.0

dB

1100

1.714

8.0

dB

1101

2.143

10.0

dB

1110

2.571

12.0

dB

1111

3.0

14.0

dB

Data Loading

The 8-bit data word is loaded

bit 7 first and bit 0 last.

Bit 7 must be a logic “1” to address the chip.

If bit 7 in the word is a logic “0” that 8-bit word will not be

executed. Figure 4 (below) shows the timing information

required to load and operate this device.

t

LLD

Load/Latch Delay

t

LLW

Load/Latch Pulse Width

t

LLO

Load/Latch Over Time

Timing

t

PWH

Serial Clock "High" Pulse Width

t

PWL

Serial Clock "Low" Pulse Width

t

DS

Data Set-up Time

t

DH

Data Hold Time