FX629 datasheet(5/10 Pages) CMLMICRO

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Codec Timing Information

Sample Rate

Bit Sequence at Decoder Input

“Run of Threes”

Output Level

(%)

(dBm0)

16kbit/s

11011011010010010010

-29.2

± 2

32kbit/s

1101101101010100100100100100101010110110

-30.0

± 2

16kbit/s

11111011010000010010

± 1

32kbits

1111110110101010000100000010010101011110

± 1

Table 1 Bit Sequence Tests and Results

at 800Hz

Digital to Analogue Performance ...... Using the bit sequence tests shown in Table 1 (below) at the

Decoder Input pin, the analogue signals measured at the Decoder Output pin are 800Hz

± 10Hz at the levels

described.

Fig.4 Codec Timing Diagrams

DECODER TIMING

ENCODER TIMING

MULTIPLEXING FUNCTION

HIGH Z

DATA TRUE TIME

DATA CLOCKED

t CL

DATA CLOCKED

t CH

t IF

t IR

PCO

t CH

ENCODER

CLOCK

ENCODER DATA

OUTPUT

DECODER

CLOCK

DECODER DATA

INPUT

ENCODER

OUTPUT

DATA ENABLE

TIMING

Clock '1' Pulse Width

Clock Rise Time

SU Data Set-up Time

SU + tH = Data True Time

1.0

µs Min.

100ns Typ.

450ns Min.

Clock '0' Pulse Width

Clock Fall Time

H Data Hold Time

PCO Clock to Output Delay Time

1.0

µs Min.

100ns Typ.

600ns Min.

750ns Max.

DR Data Rise Time

DF Data Fall Time

Xtal Input Frequency

100ns Typ.

1.024MHz.

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