FX663 datasheet(4/17 Pages) CMLMICRO

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D/663/3

1.3

Signal List

Package

D4/P3

Signal

Description

Pin No.

Name

Type

XTALN

O/P

The inverted output of the on-chip oscillator.

XTAL/CLOCK

I/P

The input to the on-chip oscillator, for external

Xtal circuit or clock.

O/P

D3, D2, D1 and D0 is a 4-bit parallel data word

output to the µController. The transmission of

data is under the control of the CSN input.

These 3-state outputs are held at high

impedance when CSN is at "1". See Bus Timing

Diagram (Figure 8).

If CSN is permanently at "0", D3, D2, D1 and D0

are permanently active. See Timing Diagram

(Figure 4 to 7).

CSN

I/P

The data output control function: this input is

provided by the µController. Data transfer

sequences are initiated, completed or aborted

by the CSN signal. See Bus Timing Diagram

(Figure 8).

IRQN

O/P

This output indicates an interrupt condition to

the µController by going to a logic "0". This is a

"wire-ORable" output, enabling the connection of

up to 8 peripherals to 1 interrupt port on the

µController. This pin has a low impedance

pulldown to logic "0" when active and a high-

impedance when inactive. An external pullup

resistor is required.

If CSN is permanently at "0", the interrupt

condition is a logic "0" pulse. See Timing

Diagram (Figure 4 to 7).

ENABLE

I/P

A low level input selects the powersave mode,

all circuits are reset and disabled. D0 - D3

outputs become high impedance. A high level

enables all circuits. (See also CSN).

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