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FMP3216DAX Datasheet(PDF) 8 Page - FIDELIX

Part # FMP3216DAX
Description  2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
PDF  11 Pages
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Manufacturer  FIDELIX [FIDELIX]
Direct Link  http://www.fidelix.co.kr
Logo FIDELIX - FIDELIX

FMP3216DAX Datasheet(HTML) 8 Page - FIDELIX

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FMP3216DAx
CMOS LPRAM
WRITE CYCLE (1) (/WE controlled, /ZZ=VIH)
tWC
Address
/CS
/UB, /LB
/WE
tWC
tCW(2)
tWR(4)
tAW
tBW
tWP(1)
WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH)
tWC
Data Out
tAS(3)
High-Z
High-Z
Data Undefined
Data Valid
tDW
tDH
tOW
tWHZ
Data in
Address
/CS
/UB, /LB
/WE
tWC
tWR(4)
tBW
tWP(1)
tDW
tDH
tCW(2)
tAS(3)
tAW
Data Out
High-Z
High-Z
Data Valid
tDW
tDH
Data in
WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH)
Address
tWC
Address
/CS
/UB, /LB
/WE
tWR(4)
tBW
tWP(1)
tDW
tDH
tCW(2)
tAW
tAS(3)
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
Data Out
High-Z
High-Z
Data Valid
Data in
Revision 0.1
Jul. 2010
8
gg
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.



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