MAG3110 datasheet(8/23 Pages) FREESCALE

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Freescale Semiconductor

MAG3110

4Functionality

MAG3110 is a small low-power, digital output, 3-axis linear magnetometer packaged in a 10 pin DFN. The device contains a

magnetic transducer for sensing and an ASIC for control and digital I2C communications.

4.1

I2C

Serial Interface

Communication with the MAG3110 takes place over an I2C bus. The MAG3110 also has an interrupt signal indicating that new

magnetic data readings are available. Interrupt driven sampling allows operation without the overhead of software polling.

4.2

Factory Calibration

MAG3110 is factory calibrated for sensitivity, offset and temperature coefficient. All factory calibration coefficients are applied

automatically by the MAG3110 ASIC before the magnetic field readings are written to registers 0x01 to 0x06 (see section 5).

There is no need for the user to apply the calibration correction in the software and the calibration coefficients are not therefore

accessible to the user.

The offset registers in the addresses 0x09 to 0x0E are not a factory calibration offset but allow the user to define a hard iron

offset which can be automatically subtracted from the magnetic field readings (see section 4.3.3).

4.3

Digital Interface

There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). External pull-

up resistors (connected to VDDIO) are needed for SDA and SCL. When the bus is free, both lines are high. The I2C interface is

compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards.

4.3.1

General I2C Operation

I2C is an asynchronous, open collector driven, addressed and packetized serial bus interface. It is capable of supporting

multiple masters and multiple slave devices on the same bus. I2C uses two bi-directional lines, the serial clock line or SCL and

the serial data line or SDA. Pull-up resistors are required on both lines.

An I2C transaction starts with a start condition (START) and ends with a stop condition (STOP). A START condition is defined

as a HIGH to LOW transition on the data line while the clock line is held HIGH. A STOP condition is defined as a LOW to HIGH

transition on the data line while the clock line is held HIGH. At all other times, the data line can only change state when the clock

line is low. If the data line changes state when the clock is high, the I2C transaction is aborted and the new start or stop condition

is recognized.

After START has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after START

condition is the slave address in the first 7 bits, and the eighth bit is the Read/Write (R/W) bit (read = 1, write = 0). The R/W bit

determines whether the I2C master intends on receiving data from the slave – Read mode or intends to transmit data to the slave

– Write mode. When an address is sent, each device on the I2C bus compares the first 7 bits after a start condition with its own

internal address. If the address matches, the device considers itself addressed by the Master and continues to respond. If the

address does not match, the device ignores further bus activity until the next start condition happens.

The ninth bit (clock pulse), following each I2C byte is for the acknowledge (ACK) bit. The master releases the SDA line during

the ACK period. Because of the pull-up resistor, the data line will tend to float high. To signal ACK back to the master, the slave

must then pull the data line low during this clock period.

The number of bytes per transfer can be unlimited. If a receiving device can't accept another complete byte of data until it has

performed some other function, it can hold the clock line, SCL, low to force the transmitter into a wait state. Data transfer only

continues when the receiver is ready for another byte and releases the data line. This delay action is called clock stretching. The

MAG3110 device does clock stretching.

A data transfer is always terminated by a STOP.

The MAG3110 I2C 7-bit device address is 0x0E. In I2C practice, the device address is shifted left by one bit field and a read/

write bit is set in the lowest bit position. The I2C 8-bit write address is 0x1C and the read address is 0x1D.

The I2C 8-bit write address is 0x3A and the read address is 0x3B. Please consult the factory for alternate addresses.

Table 8. Serial Interface Pin Description

Pin Name

Pin Description

VDDIO

IO voltage

SCL

I2C Serial Clock

SDA

I2C Serial Data

INT

Data ready interrupt pin

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