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ZXFV4089 Datasheet(PDF) 8 Page - Diodes Incorporated |
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ZXFV4089 Datasheet(HTML) 8 Page - Diodes Incorporated |
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8 / 12 page ![]() ZXFV4089 Issue 4 - December 2008 8 www.zetex.com © Diodes Incorporated 2008 www.diodes.com Figure 3 shows a portion of a typical video waveform, where the sample pulse is synchronised to fall within the back porch interval. This can for example be achieved using the Zetex ZXFV4583 sync separator to derive the pulse as in the evaluation circuit described in the data sheet for that part. Again, during the logic LOW period of the HOLD input, the waveform is driven towards VREF. Eventually, after a few line scans, the video waveform is stabilised with the back porch level equal to VREF and this condition is maintained despite any small changes in the input waveform. In the video application, the HOLD input state will be HIGH during the picture line sweep and a negative-going sampling pulse of typically 1.2µs duration will be applied during a central portion of the back porch interval, so that the back porch or 'Black' level is clamped to VREF (typically ground). Figure 3 Response to typical video signal If desired, by changing the external pulse timing the signal may be restored such that the sync tip voltage is clamped to VREF instead of the back porch. In either case, for each line scan, this gives a brightness level consistent with that of the original camera signal, despite the AC coupling. The value of the coupling capacitor affects two main characteristics of the circuit: 1. DC level acquisition change 2. DC level droop DC level acquisition change In the restore mode the available charging current, together with the capacitor value, determines the maximum DC voltage correction which can be applied at each sample. For a charging current limit of 300µA applied for 1.2µs, the charge injected is: Qmax = 300µA x 1.2µs = 360pC Then the maximum voltage shift correction is: Vmax = Qmax/C = 360pC / 0.01µF = 36mV |
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