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ADRF6801 Datasheet(PDF) 19 Page - Analog Devices

Part # ADRF6801
Description  750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF6801 Datasheet(HTML) 19 Page - Analog Devices

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ADRF6801
Rev. 0 | Page 19 of 36
Register 5—LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in
divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.
DEMOD
BIAS
ENABLE
LO
FIRST
DIVIDER
LO
IN/OUT
CTRL
LO
OUTPUT
DRIVER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DMBE
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
LDIV
LXL
LDRV C3(1) C2(0) C1(1)
LDRV
0
1
LXL
0
1
LDIV
0
1
÷ 1
÷ 2 (DEFAULT,
NECESSARY FOR VCO USE)
LO OUTPUT DRIVER
ENABLE
DRIVER OFF (DEFAULT)
DRIVER ON
DMBE
0
1
DISABLE
ENABLE (DEFAULT)
DEMOD BIAS ENABLE
LO IN/OUT CONTROL
LO OUTPUT (DEFAULT)
LO INPUT
DIVIDE RATIO
CONTROL BITS
0
0
000
00
0
00
0
0
Figure 38. LO Path and Demodulator Control Register (R5)



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