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R5F2LA52ADFP Datasheet(PDF) 13 Page - Renesas Technology Corp |
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R5F2LA52ADFP Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 106 page ![]() R01DS0011EJ0100 Rev.1.00 Page 13 of 102 Dec 21, 2010 R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 1. Overview Figure 1.6 Block Diagram of R8C/LA5A Group Watchdog timer (14 bits) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT RAM (2) Multiplier Timers Timer RB (8 bits × 2) Timer RC (16 bits × 1) Timer RH Timer RJ (16 bits × 2) R8C CPU core Memory R0H R0L R1H R2 R3 R1L A0 A1 FB SB USP ISP INTB PC FLG I/O ports A/D converter (10 bits × 7 channels) UART or clock synchronous serial I/O (8 bits × 1) I2C bus or SSU (8 bits × 1) ROM (1) Peripheral functions LCD drive control circuit Common output: Max. 4 pins Segment output: Max. 27 pins Temperature Sensor 8 2 3 Comparator B 2 ch Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. Port P0 8 Port P2 8 Port P3 8 Port P5 7 Voltage detection circuit Low-speed on-chip oscillator for watchdog timer |
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