CY2DL1504ZXCT datasheet(13/15 Pages) CYPRESS

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CY2DL1504

Document Number: 001-56312 Rev. *E

Page 13 of 15

Document History Page

Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

Document Number: 001-56312

Revision

ECN

Orig. of Change

Submission

Date

Description of Change

2782891

CXQ

10/09/09

New Datasheet.

2838613

CXQ

01/05/2010

Changed status from “ADVANCE” to “PRELIMINARY”.

Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features”

on page 1 and in tJIT in the AC Electrical Specs table on page 5.

Added tPU spec to the Operating Conditions table on page 3.

Changed max IDD spec in the DC Electrical Specs table on page 4 from

60 mA to 61 mA.

Removed VOD and ΔVOD specs from the DC Electrical Specs table on

page 4.

Changed IOZ in the DC Electrical Specs table on page 4 from min of

-10 uA to -15 uA and from max of 10 uA to 15 uA.

Added RP spec in the DC Electrical Specs table on page 4. Min = 60 kΩ,

Max = 140 k

Ω.

Added a measurement definition for CIN in the DC Electrical Specs table

on page 4.

Added VPP and ΔVPP specs to the AC Electrical Specs table on page 5.

VPP min = 250 mV and max = 470 mV; ΔVPP max = 50 mV.

Changed letter case and some names of all the timing parameters in the

AC Electrical Specs table on page 5 to be consistent with EROS.

Lowered all additive phase noise mask specs by 3 dB in the AC Electrical

Specs table on page 5.

Added condition to tR and tF specs in the AC Electrical specs table on

page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%).

Changed letter case and some names of all the timing parameters in

Figures 4, 5, 6, 7 and 9, to be consistent with EROS. Updated Figure 4

with definition for VPP and ΔVPP.

3010332

CXQ

08/18/2010

Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features”

on page 1 and in tJIT in the AC Electrical Specs table on page 5.

Added “Functional equivalent to ICS8543i” to the “Features” section.

Changed pin 13 in Figure 1 and Table 1 from VDD to VSS.

Changed pin 8 description in Table 1 from “high impedance” to “disabled”.

Added note 6 to describe IIH and IIL specs.

Removed reference to data distribution from “Functional Description”.

Changed RP for diff inputs from 100 kΩ to 150 kΩ in the Logic Block

Diagram and from 60 k

Ω min / 140 kΩ max to 90 kΩ min / 210 kΩ max

in the DC Electrical Specs table.

Split VID into separate specs in DC Electrical Specs table: 0.4 V min and

0.8 V max for LVDS, 0.4 V min and 1.0 V max for LVPECL.

Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset

to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC

Electrical Specs table.

Added “Frequency range up to 1 GHz” condition to tODC spec.

Changed tOD in the AC Electrical Specs table from 3 ns max to 5 ns max.

Added Acronyms and Ordering Code Definition.

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