33882 datasheet(18/27 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33882

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

conditions, the SO pin (not daisy chained) returns all 0s,

representing no faults. If a fault is present, a 1 is returned for

the appropriate bit. In 16-bit SPI mode, sending a double

command byte will provide a command verification byte

following the fault status byte returned from the SO pin (non-

daisy chained). With the MODE pin high, the serial output pin

tri-states. If nothing is connected to the SO pin except an

external 10 k

Ω pull-up resistor, data is read as all 1s by the

control IC.

VDD Pin

This pin is connected to the 5.0 V power supply of the

system. A decoupling capacitor is required from VDD to

ground.

PERFORMANCE FEATURES

Normal Operation

OUT0 to OUT7 are independent during normal operation.

OUT0 to OUT5 may be driven serially or by their parallel input

pins. OUT6 and OUT7 can only be controlled by their parallel

input pins. Device operation is considered normal only if the

following conditions apply:

•VPWR of 5.5 V to 24 V and VDD voltage of 4.75 V to 5.25 V.

• Junction temperatures less than 150

°C.

• For each output, drain voltage exceeds the Open Load

OFF Detection Voltage, specified in the specification table,

while the output is OFF. For open load detection, an open

condition existing for less than the Open Load Detection

time, specified in the specification table, is not considered

a fault nor is it reported to the fault status register.

•The MODE pin is held at the logic low level, keeping the

serial channel/parallel input pins in control of the eight

outputs.

Serial/Parallel Input Control

Input control is accomplished by the serial control byte

sent via the SPI port from the control IC or by the parallel

control pins for each channel. For channels 0 to 5 with serial

and parallel control the output state is determined by the OR

of the serial bit and the parallel input pin state. Serial

communication is initiated by a low state on the CS pin and

timed by the SCLK signal. After CS switches low, the IC

initiates eight or 16 clock pulses with the control bits being

available on the SI pin at the rising edge of SCLK.

The bits are transferred in descending bit-significant

order. Any fault or MODE indications on bits returned are logic

[1]s. The last six bits are the command signals to the six

outputs. Upon completion of the serial communication the CS

pin will switch high. This terminates the communication with

the slave device and loads the control bits just received to the

output channels. Upon device power-up, the serial register is

cleared.

In the application for non-daisy chain configurations, the

number of SPI devices available to be driven by the SO pin is

limited to eight devices.

Serial Status Output

Serial output information sent on the SPI port is a check on

the fault status of each output channel as well as a check for

MODE

initiation. Serial command verification is also possible.

SO Pin Operation

The SO pin provides SPI status, allowing daisy chaining.

The status bits returned to the IC are the fault register bits

with logic [1]s indicating a fault on the designated output or

MODE

if all bits return logic [1] (with a 10 k

Ω pull-up resistor

on the SO pin). A command verification is possible if the SPI

mode is switched to 16 bits. The first byte (8 bits) returned

would be the fault status, while the second byte returned

would be the first byte sent feeding through the 33882 IC.

The second command byte sent would be latched into the

33882 IC. The CS pin switching low indicates the device is

selected for serial communication with the IC. Once CS

switches low, the fault status register cannot receive new

fault information and serial communication begins. As the

control bits are clocked from the IC MSB first, they are

received on rising SCLK edges at the SI pin.

The fault status bits transition on the SO pin on falling

SCLK edges and are sampled on rising SCLK edges at the

input pin of the IC SPI device. When the command bit

transmissions for serial communication are complete, the CS

pin is switched high. This terminates communication with the

device. The SO pin tri-states, the fault status register is

opened to accept new fault information, and the transmitted

command data is loaded to the outputs. At the same time, the

IC can read the status byte it received.

Daisy Chain Operation (Only Possible with SO Pin)

Daisy chain configurations can be used with the SO pin to

save CS outputs on the IC. Clocking and pin operations are

as defined in the SO Pin Operation paragraph. For daisy

chaining two 8-bit devices, a 16-bit SPI command is sent, the

first command byte for the second daisy chain device and the

second command byte for the first daisy chain device. A

command verification is possible if the SPI mode is switched

to 32 bits. The first word sent is command verification data

fed through the two 33882 ICs. Data returned in the 32 bits is

the two fault status bytes, followed by the first word sent. Bits

sent out are sampled on rising SCLK edges at the input pin

of the next IC in the daisy chain.

Note Because SO pins of the 33882 ICs are tri-stated,

any device receiving its SPI data from a previous 33882 IC

SO pin in a daisy chain will not receive data if the MODE pin

is low. This prohibits setting SPI-controlled channels ON with

a SPI command while the MODE pin is low. Therefore, all

channels remain OFF when the MODE pin changes from low

to high at vehicle power-up.

33882 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

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