DSPIC30F2010 datasheet(117/202 Pages) MICROCHIP

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DS70118J-page 117

dsPIC30F2010

18.7.3.3

600 ksps Configuration Items

The following configuration items are required to

achieve a 600 ksps conversion rate.

• Comply with conditions provided in Table 18-2

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 register to

enable the auto-convert option

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register

• Enable sequential sampling by clearing the

SIMSAM bit in the ADCON1 register

• Enable at least two sample and hold channels by

writing the CHPS<1:0> control bits in the

ADCON2 register

• Write the SMPI<3:0> control bits in the ADCON2

between interrupts. At a minimum, set

SMPI<3:0> = 0001 since at least two sample and

hold channels should be enabled

• Configure the A/D clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

Select at least two channels per analog input pin by

writing to the ADCHS register.

18.8

A/D Acquisition Requirements

The analog input model of the 10-bit ADC is shown in

Figure 18-3. The total sampling time for the A/D is a

function of the internal amplifier settling time, device

VDD and the holding capacitor charge time.

For the A/D converter to meet its specified accuracy, the

charge holding capacitor (CHOLD) must be allowed to

fully charge to the voltage level on the analog input pin.

The

source

impedance

(RS),

the

interconnect

impedance (RIC), and the internal sampling switch

(RSS) impedance combine to directly affect the time

required to charge the capacitor CHOLD. The combined

impedance of the analog sources must therefore be

small enough to fully charge the holding capacitor within

the chosen sample time. To minimize the effects of pin

leakage currents on the accuracy of the A/D converter,

the maximum recommended source impedance, RS, is

5 k

Ω. After the analog input channel is selected

(changed), this sampling function must be completed

prior to starting the conversion. The internal holding

capacitor will be in a discharged state prior to each

sample operation.

The user must allow at least 1 TAD period of sampling

time, TSAMP, between conversions to allow each sam-

ple to be acquired. This sample time may be controlled

manually in software by setting/clearing the SAMP bit,

or it may be automatically controlled by the A/D con-

verter. In an automatic configuration, the user must

allow enough time between conversion triggers so that

the minimum sample time can be satisfied. Refer to the

Electrical Specifications for TAD and sample time

requirements.

FIGURE 18-3:

ADC ANALOG INPUT MODEL

12 x 600,000

= 138.89 ns

CPIN

ANx

VT = 0.6V

I leakage

RIC

≤250Ω

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

VDD

= 4.4 pF

± 500 nA

Legend: CPIN

I leakage

RIC

RSS

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch resistance

= sample/hold capacitance (from DAC)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs

≤5 kΩ.

RSS

≤3 kΩ

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