MIC59P60

4

August 2001

MIC59P60

Micrel

Timing Conditions

A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns

B. Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns

C. Minimum Data Pulse Width ..................................................................................................................................... 150 ns

D. Minimum Clock Pulse Width .................................................................................................................................... 150 ns

E. Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns

F. Minimum Strobe Pulse Width ................................................................................................................................... 100 ns

G. Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns

SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input

pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL

DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Holding CLEAR high results in a data

logic "0" being clocked into the shift register, turning off respective channels.

Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).

The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed

(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.

When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches

or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OE/RESET pulse

resets the FLAG and the output after a current shutdown fault. Over-temperature faults are not latched and require no reset

pulse.

CLOCK

DATA IN

STROBE

OUTPUT

ENABLE

D

B

A

E

C

G

OUTN

F

MIC59P60 Truth Table

Serial

Shift Register Contents

Serial

Latch Contents

Output Contents

Data

Clear Clock

Data

Strobe

Output

Input

Input Input

Output

Input

……

HH

LL

XR1

R2

H

OOO ……

OL

XXX ……

XX

L

XX

X

……

XH

H

H

H

…… H

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

O = Output OFF