LTC2182 datasheet(18/36 Pages) LINER

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LTC2142-12/

LTC2141-12/LTC2140-12

21421012p

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

D1_0_1–/D1_0_1+ to D1_10_11–/D1_10_11+ (Pins 47/48,

49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double

Data Rate Digital Outputs. Two data bits are multiplexed

onto each differential output pair. The even data bits (D0,

D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The

odd data bits (D1, D3, D5, D7, D9, D11) appear when

CLKOUT+ is high.

OF2_1–/OF2_1+ (Pins 59/60):

Over/Underflow Digital

Output. OF2_1+ is high when an overflow or underflow

has occurred. The over/underflow for both channels

are multiplexed onto this pin. Channel 2 appears when

CLKOUT+ is low, and Channel 1 appears when CLKOUT+

is high.

DIFF

REF

AMP

REF

BUF

2.2μF

0.1μF

INTERNAL CLOCK SIGNALS

REFH

REFL

CLOCK/DUTY

CYCLE

CONTROL

RANGE

SELECT

1.25V

REFERENCE

ENC+

REFH

REFL

ENC–

CORRECTION

LOGIC

SDO

OGND

OF1

OVDD

D1_11

CLKOUT–

CLKOUT+

D1_0

21421012 F01

SENSE

VREF

CH 1

ANALOG

INPUT

2.2μF

VCM1

0.1μF

VDD/2

OUTPUT

DRIVERS

MODE

CONTROL

REGISTERS

SCK

PAR/SER

SDI

•

GND

S/H

12-BIT

ADC CORE

CH 2

ANALOG

INPUT

S/H

12-BIT

ADC CORE

VCM2

0.1μF

OF2

D2_11

D2_0

•

VDD

PIN FUNCTIONS

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