PIC16F1847 datasheet(131/408 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

Preliminary

DS41453B-page 131

PIC16(L)F1847

13.0

INTERRUPT-ON-CHANGE

The PORTB pins can be configured to operate as

Interrupt-on-change (IOC) pins. An interrupt can be

generated by detecting a signal that has either a rising

edge or a falling edge. Any individual PORTB pin can

configured to generate an interrupt.

The

interrupt-on-change module has the following features:

• Interrupt-on-change enable (Master Switch)

• Individual pin configuration

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 13-1 is a block diagram of the IOC module.

13.1

Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCE bit of the INTCON register must be set. If the IOCE

bit is disabled, the edge detection on the pin will still

occur, but an interrupt will not be generated.

13.2

Individual Pin Configuration

For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated IOCBPx bit of the IOCBP

the associated IOCBNx bit of the IOCBN register is set.

A pin can be configured to detect rising and falling

edges simultaneously by setting both the IOCBPx bit

and the IOCBNx bit of the IOCBP and IOCBN registers,

respectively.

13.3

Interrupt Flags

The IOCBFx bits located in the IOCBF register are

status flags that correspond to the Interrupt-on-change

pins of the port. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCE

bit is set. The IOCF bit of the INTCON register reflects

the status of all IOCBFx bits.

13.4

Clearing Interrupt Flags

The individual status flags, (IOCBFx bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 13-1:

13.5

Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCE bit is set.

If an edge is detected while in Sleep mode, the IOCBF

executed out of Sleep.

FIGURE 13-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

MOVLW

0xff

XORWF

IOCBF, W

ANDWF

IOCBF, F

RBx

From all other IOCBFx

individual pin detectors

IOCBNx

IOCBPx

Q2 Clock Cycle

IOCE

IOC Interrupt to

CPU Core

IOCBFx

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