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33905 Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc

Part # 33905
Description  SBC Gen2 with CAN High Speed and LIN Interface
PDF  104 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33905 Datasheet(HTML) 75 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
75
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
WATCHDOG AND MODE REGISTERS
Table 24. Watchdog Refresh Register, watchdog(34)
MOSI First Byte [15-8]
[b_15 b_14] 01_101 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 101 P
0
0
0
0
0
0
0
0
Default state
0
0
0
0
0
0
0
0
Condition for default
POR
Notes
34.
The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to
transition from INIT Mode to Normal Mode, and from Normal Request Mode to Normal Mode (after a Wake-Up of a reset)
.
Table 25. MODE Register, MODE
MOSI First Byte [15-8]
[b_15 b_14] 01_110 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 110 P
mode[4]
mode[3]
mode[2]
mode[1]
mode[0]
Rnd_b[2]
Rnd_b[1]
Rnd_b[0]
Default state
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 26. LP VDD OFF Selection and FWU / Cyclic Sense Selection
b7, b6, b5, b4, b3
FWU
Cyclic Sense
0 1100
OFF
OFF
0 1101
OFF
ON
0 1110
ON
OFF
0 1111
ON
ON
Table 27. LP VDD ON selection and operation mode
b7, b6, b5, b4, b3
FWU
Cyclic Sense
Cyclic INT
Watchdog
1 0000
OFF
OFF
OFF
OFF
1 0001
OFF
OFF
OFF
ON
1 0010
OFF
OFF
ON
OFF
1 0011
OFF
OFF
ON
ON
1 0100
OFF
ON
OFF
OFF
1 0101
OFF
ON
OFF
ON
1 0110
OFF
ON
ON
OFF
1 0111
OFF
ON
ON
ON
1 1000
ON
OFF
OFF
OFF
1 1001
ON
OFF
OFF
ON
1 1010
ON
OFF
ON
OFF
1 1011
ON
OFF
ON
ON
1 1100
ON
ON
OFF
OFF
1 1101
ON
ON
OFF
ON
1 1110
ON
ON
ON
OFF
1 1111
ON
ON
ON
ON
b2, b1, b0
Random Code inverted, these 3bits are the inverted bits obtained from the
previous SPI command. The usage of these bits are optional and must be
previously selected in the INIT MISC register [See bit 7 (LPM w RNDM) in
Table 18]



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