MM912G634CV2AP datasheet(74/345 Pages) FREESCALE

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Wake-up / Cyclic Sense

MM912_634 Advance Information, Rev. 4.0

Freescale Semiconductor

4.9.2.3

Wake-up Source Register (WSR)

Table 97. TCR - Register Field Descriptions

Field

Description

7-4

FWM

Forced Wake-up Multiplicator - Configures the multiplicator for the forced wake-up. The selected multiplicator (FWM!=0)

will force a wake-up every FWM x CST ms. With this implementation, Forced and Cyclic wake-up can be performed in

parallel with the cyclic sense period <= the forced wake-up period.

0000 - Forced Wake-up = Off

0001 - 1x

0010 - 2x

0011 - 4x

0100 - 8x

0101 - 16x

0110 - 32x

0111 - 64x

1000 - 128x

1001 - 256x

1010 - 512x

1011 - 1024x

11xx - not implemented (Forced Wake Multiplicator = 1024x)

3-0

CST

Cyclic Sense Timing(71)

0000 - 1.0 ms

0001 - 2.0 ms

0010 - 5.0 ms

0011 - 10 ms

0100 - 20 ms

0101 - 50 ms

0110 - 100 ms

0111 - 200 ms

1000 - 500 ms

1001 - 1000 ms

1010 - 1111 - not implemented (Cyclic Sense Timing = 1000 ms)

Note:

71.

Cyclic Sense Timing with Accuracy CSAC and CSACT.

Table 98. Wake-up Source Register (WSR)

Offset(72) 0x14

Access: User read

654

FWU

LINWU

L5WU

L4WU

L3WU

L2WU

L1WU

L0WU

Note:

72.

Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 99. WSR - Register Field Descriptions

Field

Description

7 - FWU

Forced Wake-up - Wake-up caused by a forced wake-up

6 - LINWU

LIN Wake-up - Wake-up caused by a LIN wake-up

5 - L5WU

L5 Wake-up - Wake-up caused by a state change of the L6 Input

4 - L4WU

L4 Wake-up - Wake-up caused by a state change of the L5 Input

3 - L3WU

L3 Wake-up - Wake-up caused by a state change of the L4 Input

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