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TLE8262-2E Datasheet(PDF) 83 Page - Infineon Technologies AG |
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TLE8262-2E Datasheet(HTML) 83 Page - Infineon Technologies AG |
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83 / 94 page  Data Sheet 83 Rev. 1.0, 2009-05-26 TLE8262-2E Serial Peripheral Interface 15.6.2 Read Only command In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read). With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The watchdog can also be triggered with a Read Only command. The Read Only command delivers the information requested with the Configuration Select in the same SPI command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI command. Figure 40 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in difference to the register description. Figure 40 Read Only Command Figure 41 shows an example of an SPI write access in normal mode for comparison. The requested information is sent out with the next SPI command. Figure 41 Write Command WK state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DI MS0MS1 MS2CS0 CS1 CS2 WD refresh Configuration Select Mode Selection Bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DI MS0 MS1 MS2 CS0 CS1 CS2 WD refresh Configuration Select Mode Selection Bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DO MS0MS1 MS2CS0 CS1 CS2 Configuration Select Mode Selection Bits 1 1 1 0 0 0 x x x x x x x x x x WK state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DO MS0 MS1 MS2 CS0 CS1 CS2 Configuration Select Mode Selection Bits 1 1 0 1 0 0 x x x x x x x x x x 1 1 0 0 0 0 x x x x x x x x x x 1 1 0 1 1 1 x x x x x x x x x x TIME WK state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DI MS0MS1 MS2CS0 CS1 CS2 WD refresh Configuration Select Mode Selection Bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DI MS0 MS1 MS2 CS0 CS1 CS2 WD refresh Configuration Select Mode Selection Bits 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DO MS0MS1 MS2CS0 CS1 CS2 Configuration Select Mode Selection Bits 1 1 0 0 0 0 x x x x x x x x x x WK state 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Configuration Registers DO MS0 MS1 MS2 CS0 CS1 CS2 Configuration Select Mode Selection Bits 1 1 0 0 0 0 x x x x x x x x x x 1 1 0 1 0 0 x x x x x x x x x x 1 1 0 1 1 1 x x x x x x x x x x TIME |
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