CY2XF32

Document Number: 001-53147 Rev. *D

Page 2 of 10

Pinouts

Figure 1. Pin Diagram – 6 Pin Ceramic LCC

Functional Description

The FS0 and FS1 pins select between four different output

frequencies, as shown in Table 2. Frequency margining is a

common application for this feature. One frequency is used for

the standard operating mode of the device, while the other

frequencies are available for margin testing, either during

product development or in system manufacturing test.

When changing the output frequency, the frequency transition is

not guaranteed to be smooth. There can be frequency excur-

sions beyond the start frequency and the new frequency.

Glitches and runt pulses are possible, and time must be allowed

for the PLL to relock.

Pin 1 is programmed to function as either OE (output enable) or

PD# (power-down, active low). The OE function is used to enable

or disable the CLK output very quickly, but it does not reduce

core power consumption. The PD# function puts the device into

a low power state, but the wake up takes longer because the PLL

must reacquire lock. Details are shown in Table 3 and Table 4.

1

3

OE/PD#

VSS

VDD

CLK

6

4

2

5FS0

FS1

Table 1. Pin Definitions – 6-pin Ceramic LCC

Pin

Name

I/O Type

Description

1

OE/PD#

CMOS Input

Output Enable or Power-down: Functionality is a programming option; see Table 3 and

Table 4 for details.

2, 5

FS1, FS0

CMOS Input

Frequency Select.

4

CLK

CMOS Output

Clock Output.

6

VDD

Power

Supply Voltage: 2.5 V or 3.3 V.

3

VSS

Power

Ground.

Table 2. Frequency Select

FS1

FS0

Output Frequency

0

0

Frequency 0

0

1

Frequency 1

1

0

Frequency 2

1

1

Frequency 3

Table 3. Output Enable Operation

OE

PLL & Xtal Oscillator

Output Buffer

0Active

Off

1

Active

On

Table 4. Power-down Operation

PD#

PLL & Xtal Oscillator

Output Buffer

0Off

Off

1

Active

On

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